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3D TSV:重要课题的考察与市场的分析
市场调查报告书
商品编码
1266864

3D TSV:重要课题的考察与市场的分析

3-D TSV: Insight On Critical Issues and Market Analyses
出版日期: | 出版商: Information Network | 英文 | 商品交期: 2-3个工作天内

价格

本报告提供3D TSV市场相关调查，TSV IC及其製造所使用的设备与材料的分析。

目录

第1章 简介

第2章 重要课题的考察

  • 3D TSV的促进因素
  • 使用了TSV的3D IC的优点
  • 成本效率高的3D晶片堆迭技术的要求
  • TSV技术的课题
  • TSV供应链的课题
  • 3D封装技术的限制
    • 温度控管
    • 成本
    • 设计的复杂度
    • 交期

第3章 成本结构

  • 3D晶片堆迭的成本结构
  • 拥有的成本

第4章 重要的处理技术

  • 简介
  • 铜镀金
  • 微影製程
    • 光微影製程
    • 压印微影
    • 抗蚀剂涂布
  • 电浆蚀刻技术
  • 剥离/清洗
  • 薄的晶圆的连接
  • 晶圆的薄化/CMP
  • 堆迭
  • 测量/检验

第5章 重要的开发市场区隔的评估

  • 简介
  • 导孔(Vias)最初
    • 设备的要求
    • 材料的要求
  • VIA Middle
    • 设备的要求
    • 材料的要求
  • 后导孔(Via Last)
    • 设备的要求
    • 材料的要求
  • 内插器

第6章 参与企业的简介

  • 晶片厂商/包装住宅/服务
  • 设备供应商
  • 材料供应商
  • 研究开发

第7章 市场分析

  • TSV设备的蓝图
  • TSV设备的预测
  • 设备的预测
  • 材料的预测

Through-Silicon Via (TSV) is a vertical electrical connection that passes completely through a silicon wafer or chip to create 3D ICs or packages. The drivers for market adoption of 3D ICs are increased performance, reduced form factor and cost reduction. TSV provides the high-bandwidth interconnection between stacked chips. The different TSV processes, which are more complex than initially anticipated, are analyzed.

This report analyzes the market for TSV ICs by units and wafers, and for equipment and materials used in their manufacture.

Table of Contents

Chapter 1. Introduction

Chapter 2. Insight Into Critical Issues

  • 2.1. Driving Forces In 3-D TSV
  • 2.2. Benefits of 3-D ICs With TSVs
  • 2.3. Requirements For A Cost Effective 3-D Die Stacking Technology
  • 2.4. TSV Technology Challenges
  • 2.5. TSV Supply Chain Challenge
  • 2.6. Limitations of 3-D Packaging Technology
    • 2.6.1. Thermal Management
    • 2.6.2. Cost
    • 2.6.3. Design Complexity
    • 2.6.4. Time to Delivery

Chapter 3. Cost Structure

  • 3.1. Cost Structure of 3-D chip Stacks
  • 3.2. Cost of Ownership

Chapter 4. Critical Processing Technologies

  • 4.1. Introduction
  • 4.2. Cu Plating
  • 4.3. Lithography
    • 4.3.1. Optical Lithography
    • 4.3.2. Imprint Lithography
    • 4.3.3. Resist Coat
  • 4.4. Plasma Etch Technology
  • 4.5. Stripping/Cleaning
  • 4.6. Thin Wafer Bonding
  • 4.7. Wafer Thinning/CMP
  • 4.8. Stacking
  • 4.9. Metrology/Inspection

Chapter 5. Evaluation Of Critical Development Segments

  • 5.1. Introduction
  • 5.2. Via-first
    • 5.2.1. Equipment Requirements
    • 5.2.2. Material Requirements
  • 5.3. Via-Middle
    • 5.3.1. Equipment Requirements
    • 5.3.2. Material Requirements
  • 5.4. Via-Last
    • 5.4.1. Equipment Requirements
    • 5.4.2. Material Requirements
  • 5.5. Interposers

Chapter 6. Profiles Of Participants

  • 6.1. Chip Manufacturers/Packaging Houses/Services
  • 6.2. Equipment Suppliers
  • 6.3. Material Suppliers
  • 6.4. R&D

Chapter 7. Market Analysis

  • 7.1. TSV Device Roadmap
  • 7.2. TSV Device Forecast
  • 7.3. Equipment Forecast
  • 7.4. Material Forecast

LIST OF TABLES

  • 1.1. 3-D Mass Memory Volume Comparison Between Other Technologies And TI's 3-D Technology
  • 1.2. 3-D Mass Memory Weight Comparison Between Other Technologies And TI's 3-D Technology
  • 3.1. Cost Of Ownership Comparison
  • 4.1. Via Middle Metrology/Inspection Requirements
  • 4.2. Via Last Metrology/Inspection Requirements
  • 7.1. Forecast Of TSV Devices By Units
  • 7.2. Forecast Of TSV Devices By Wafers
  • 7.3. Forecast Of TSV Equipment by Type

LIST OF FIGURES

  • 1.1. 3-D Technology On Dram Density
  • 1.2. 3-D Through-Silicon Via (TSV)
  • 1.3. Graphical Illustration Of The Silicon Efficiency Between MCMs And 3-D Technology
  • 1.4. Silicon Efficiency Comparison Between 3D Packaging Technology and Other Conventional Packaging Technologies
  • 2.1. TSV Fabrication Process Challenges
  • 2.2. TSV Fabrication Process Challenge - Cu Protrusion
  • 2.3. TSV Reliability Challenges
  • 2.4. Via Middle Process Integration Challenges
  • 2.5. Via Middle Process Integration Challenges
  • 3.1. Cost Structure of D2W and W2W
  • 3.2. Assembly Cost Analysis
  • 3.2. Cost Structure Of Different Vias And Tools
  • 3.3. Cost Of Ownership For 5 X 50 TSV VIA Middle
  • 3.4. Cost Of CMP For TSV VIA Middle Process
  • 3.5. Cost Of Ownership For 10 X 100 TSV Via Middle
  • 3.6. Cost Structure Of TSVs 5 X 50 µm
  • 3.7. Interposer TSV: Upscaling To 10 X 100 µm
  • 3.8. TSV Downscaling To 3x50 µm
  • 3.9. Cost Structure Of Different Vias And Tools
  • 3.10. Via First Cost Of Ownership
  • 3.11. Via First Cost Of Ownership Front And Back Side
  • 3.12. Via First Process Flow
  • 3.13. iTSV Versus pTSV Cost Of Ownership
  • 3.14. Effect Of TSV Depth And Diameter On Cost
  • 4.1. Illustration Of Bosch Process
  • 4.2. Key Via Middle TSV Process Steps
  • 4.3. Key Last TSC Process Steps
  • 5.1. VIA First, Middle, And Last Process Flows
  • 5,2. VIA First TSV Process Flow
  • 5.3. VIA Middle TSV Process Flow
  • 5.4. Soft Reveal Process
  • 5.5. VIA Last TSV Process Flow
  • 5.6. Comparison Between 2.5D And 3D
  • 5.7. TSV Interposer Cross Sectional Schematic With RDL Layer
  • 5.8. Process Flow For RDL And UBM
  • 7.1. Leading Edge TSV Roadmap
  • 7.2. Forecast Of TSV Devices By Units
  • 7.3. Forecast Of TSV Devices By Wafers
  • 7.4. Forecast Of TSV Equipment by Type
  • 7.5. Forecast Of TSV Materials