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高密度实装(MCM，MCP，SIP，3D-TSV):市场分析及技术趋势
市场调查报告书
商品编码
1266873

高密度实装(MCM，MCP，SIP，3D-TSV):市场分析及技术趋势

High-Density Packaging (MCM, MCP, SIP, 3D-TSV): Market Analysis and Technology Trends
出版日期: | 出版商: Information Network | 英文 | 商品交期: 2-3个工作天内

价格

本报告提供高密度实装的相关调查，牵引行动及IoT的先进封装技术解决方案，对更高的性能和密度的包装趋势解说。还有技术性课题和趋势，竞争情形，市场预测等彙整资料。

目录

第1章 简介

第2章 摘要整理

第3章 技术课题和趋势

  • HDP技术概要
  • 整合的技术性规定
  • HDP的经济优点
  • 技术问题
  • 3D模组
  • 超导互连
  • KGD
  • 系统级封装(SIP)
  • 多晶片包装
  • 迭合式封装(PoP)

第4章 用途

  • 半导体产业，各最终市场
    • 应用处理器
    • 微处理器
    • 可程式规划逻辑元件(PLD)
    • 类比设备
    • DRAM和NAND
  • 半导体产业，各最终市场
    • 军事、航太
    • 电脑、週边设备
    • 通讯
    • 消费者
    • 产业

第5章 竞争环境

第6章 3-D-TSV技术

  • 3D-TSV的促进因素
  • 3D包装的多样性
  • TSV流程
  • 重要的处理技术
  • 用途
  • 3-D封装技术的限制
  • 企业简介

第7章 市场预测

  • 多晶片模组概要
  • 促进因素
  • 系统级封装(SiP)
  • 覆晶/晶圆级构装
  • 全球IC市场预测
  • 全球包装市场预测
  • 全球MCM市场预测

The explosion of applications in the consumer and mobile space, internet of things (IoT) and the slowdown of Moore's law have been driving many new trends and innovations in packaging. The semiconductor industry now has to focus on system scaling and integration to meet the ever-increasing electronic system demands for performance and functionality, and for reduction of system form factor, system power consumption and system cost. This paradigm shift from chip-scaling to system-scaling will re-invent microelectronics, continue driving system bandwidth and performance, and help sustain Moore's Law. The challenge for semiconductor industry is to develop a disruptive packaging technology platform capable of achieving these goals.

This report discusses the packaging trends for higher performance and density driving advanced packaging technology solutions for mobile and IoT applications. One of the key enabling technologies to achieve these goals is thin 3D-packaging with integration. Developments have lately been made with various embedding technologies, such as eWLB/Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes, at which most R&D is concentrated in the commercialization of 2.5D IC's (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.

Table of Contents

Chapter 1. Introduction

Chapter 2. Executive Summary

  • 2.1. Summary of Technology Issues
  • 2.2. Summary of Market Forecasts

Chapter 3. Technology Issues and Trends

  • 3.1. Overview of HDP Technology
    • 3.1.1. Need for Multiple IC Integration
    • 3.1.2. Challenges of Multiple IC Integration
  • 3.2. Technical Constraints of Integration
  • 3.3. Economic Benefits of HDP
  • 3.4. Technology Issues
    • 3.4.1. Substrates
    • 3.4.2. Conductors
    • 3.4.3. Dielectrics
    • 3.4.4. Vias
    • 3.4.5. Die Attachment
    • 3.4.6. Next Level Interconnection
    • 3.4.7. Thermal Management
    • 3.4.8. Test and Inspection
    • 3.4.9. Design
  • 3.5. 3-D Modules
  • 3.6. Superconducting Interconnects
  • 3.7. Known Good Die
  • 3.8. System In Package (SIP)
  • 3.9. Multichip Package
  • 3.10. Package-On-Package (PoP)

Chapter 4. Applications

  • 4.1. Semiconductor Industry by End Market
    • 4.1.1. Application Processors
    • 4.1.2. Microprocessors
    • 4.1.3. Programmable Logic Devices (PLDs)
    • 4.1.4. Analog Devices
    • 4.1.5. DRAM and NAND
  • 4.2. Semiconductor Industry by End Market
    • 4.2.1. Military and Aerospace
    • 4.2.2. Computer and Peripheral Equipment
    • 4.2.3. Communications
    • 4.2.4. Consumer
    • 4.2.5. Industrial

Chapter 5. Competitive Environment

  • 5.1. Overview of the HDP Competitive Environment
  • 5.2. Joint Ventures and Cooperative Agreements
  • 5.3. HDP Manufacturers

Chapter 6. 3-D-TSV Technology

  • 6.1. Driving Forces In 3D-TSV
  • 6.2. 3-D Package Varieties
  • 6.3. TSV Processes
  • 6.4. Critical Processing Technologies
    • 6.4.1. Plasma Etch Technology
    • 6.4.2. Cu Plating
    • 6.4.3. Thin Wafer Bondling
    • 6.4.4. Wafer Thinning/CMP
    • 6.4.5. Lithography
  • 6.5. Applications
  • 6.6. Limitations Of 3-DPackaging Technology
    • 6.6.1. Thermal Management
    • 6.6.2. Cost
    • 6.6.3. Design Complexity
    • 6.6.4. Time To Delivery
  • 6.7. Company Profiles

Chapter 7. Market Forecast

  • 7.1. Overview of Multichip Modules
  • 7.2. Driving Forces
  • 7.3. System-in-Package (SiP)
  • 7.4. Flip Chip/Wafer Level Packaging
  • 7.5. Worldwide IC Market Forecast
  • 7.6. Worldwide Packaging Market Forecast
  • 7.7. Worldwide MCM Market Forecast
    • 7.7.1. Worldwide Forecast By Substrate Type
    • 7.7.2. Worldwide 3-D Through Silicon Via (TSV) Market

List of Tables

  • 3.1. Multichip Modules Vs. Circuit Board Assemblies
  • 3.2. MCM Cost Comparison
  • 3.3. Substrate Technology Features
  • 3.4. Metal Conductors in MCMs
  • 3.5. Comparison of Thin-Film and Thick-Film Technologies
  • 3.6. Characteristics of Dielectric Materials
  • 3.7. CTE of Common Substrates and Adhesives
  • 3.8. Density Comparisons of Single Package and 3-D MCM
  • 4.1. DRAM Supply Forecasts
  • 4.2. DRAM Demand Forecasts
  • 4.3. DRAM Demand Forecasts
  • 4.4. NAND Supply Forecasts
  • 4.5. NAND Demand Forecasts
  • 4.6. NAND Demand Forecasts
  • 4.7. PC Unit Shipment Forecast, 2011-2014
  • 5.1. MCM Manufacturers
  • 6.1. 3-D Mass Memory Volume Comparison Between Other Technologies and TI's 3D Technology In Cm3/Gbit
  • 6.2. 3-D Mass Memory Weight Comparison Between Other Technologies and TI's 3D Technology In Grams3/Gbit
  • 7.1. Worldwide IC Package Market Forecast
  • 7.2. Worldwide MCM Market

List of Figures

  • 1.1. Schematic Cross-Section View Of An MCM-D
  • 1.2. Cross-Section Of The RF And Microwave MCM-D Structure
  • 1.3. Thin Film Layers On The Planarized Core Layer Of MCM-SL/D Technology
  • 1.4. Flip Chip MCP
  • 1.5. SIP Cross Section
  • 3.1. IC Packaging Trends
  • 3.2. Technology Tree For HDP Types
  • 3.3. Form Factor Decrease By Package Type
  • 3.4. High Power Package Technology Roadmap
  • 3.5. Comparison Between Wire Bonding And Bump
  • 4.1. PoP 3chipstack Package
  • 4.2. Application Processor Revenue
  • 4.3. MPU Unit Shipments And Growth Trends
  • 4.4. ASIC and ASSP Design Starts
  • 4.5. PLD Share of Revenue by End Market
  • 4.6. Analog IC Revenue
  • 4.7. FCFBGA Memory Package
  • 4.8. FBGA 2-Chip Memory Package
  • 4.9. FBGA QDP Memory Package
  • 4.10. Semiconductor Unit Demand By End Market
  • 4.11. Military and Aerospace Semiconductor Revenue
  • 4.12. Server shipments
  • 4.13. Wireless semi revenue
  • 4.14. Silicon Content Of Mobile Phones
  • 4.15. Consumer Semi Revenue
  • 4.16. Average Semi Content By Application
  • 4.17. Automotive Semiconductor Revenue
  • 4.18. Industrial Semiconductor Revenue
  • 6.1. 3-D Technology On DRAM Density
  • 6.2. 3-D Through-Silicon Via (TSV)
  • 6.3. Graphical Illustration Of The Silicon Efficiency Between MCMs And 3D Technology
  • 6.4. Silicon Efficiency Comparison Between 3D Packaging Technology And Other Conventional Packaging Technologies
  • 6.5. 3D Packages
  • 6.6. Via First, Middle, And Last Process Flows
  • 6.7. Via First TSV Process Flow
  • 6.8. New Applications Driving TSV Growth
  • 6.9. Projection Of TSV Applications And Process Requirements
  • 6-10. 3-D Technology For DRAM
  • 6.11. Moore's Law For Active Element Density
  • 7.1. Various System-In-Package (SiP) Applications
  • 7.2. SiP Structures
  • 7.3. Wire Bond Versus Flip Chip
  • 7.4. Flip Chip And Wire Bond Equipment Forecast
  • 7.5. Growth In Copper Wire Bonding
  • 7.6. WLP Demand By Devices
  • 7.7. WLP Demand By Wafers
  • 7.8. Projection of 3-D TSV Applications And Process Requirement
  • 7.9. Market Forecast of 3-D TSV Wafers
  • 7.10. Market Forecast of 3-D TSV Wafers